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| rev 1.0 data sheet no. pd60338 irmck311 dual channel sensorless motor control ic for appliances features ? mce tm (motion control engine) - hardware based computation engine for high efficiency sinusoidal sensorless control of permanent magnet ac motor ? integrated power factor correction control ? supports both interior and surface permanent magnet motors ? built-in hardware peripheral for single shunt current feedback reconstruction ? no external current or voltage sensing operational amplifier required ? dual channel three/two-phase space vector pwm ? three-channel analog output (pwm) ? embedded 8-bit high speed microcontroller (8051) for flexible i/o and man-machine control ? jtag programming port for emulation/debugger ? two serial communication interface (uart) ? i 2 c/spi serial interface ? watchdog timer with independent analog clock ? three general purpose timers/counters ? two special timers: periodi c timer, capture timer ? internal ?one-time progr ammable? (otp) memory and internal ram for final production usage ? pin compatible with irmcf311 ram version ? 1.8v/3.3v cmos product summary maximum crystal frequency 60 mhz maximum internal clock (sysclk) frequency 128 mhz maximum 8051 clock frequency 33 mhz sensorless control computation time 11 sec typ mce tm computation data range 16 bit signed 8051 otp program memory 56k bytes mce program and data ram 8k bytes gatekill latency (digital filtered) 2 sec pwm carrier frequency counter 16 bits/ sysclk a/d input channels 6 a/d converter resolution 12 bits a/d converter conversion speed 2 sec 8051 instruction execution speed 2 sysclk analog output (pwm) resolution 8 bits uart baud rate (typ) 57.6k bps number of i/o (max) 14 package (lead-free) qfp64 operating temperature -40c ~ 85c description irmck311 is a high performance otp based motion control ic designed primarily for appliance applications. irmck311 is designed to achieve low cost and high per formance control solutions for advanced inverterized appliance motor control. irmck311 contains two computation engi nes. one is motion control engine (mce tm ) for sensorless control of permanent magnet motors; the other is an 8-bit hi gh-speed microcontroller (8051). both com putation engines are integrated into one monolithic chip. the mce tm contains a collection of control elements such as proportional plus integral, vector rotator, angle estimator, multiply/divide, low loss svpwm, single shunt ifb. t he user can program a moti on control algorithm by connecting these control elements using a graphic compiler. key components of t he sensorless control al gorithms, such as the angle estimator, are provided as complete pre-defined control blocks impl emented in hardware. a unique analog/digital circuit and algorithm to fully support single shunt current rec onstruction is also provided. the 8051 microcontroller performs 2- cycle instruction execution (16mips at 33mhz). the mce and 8051 microcontrolle r are connected via dual port ram to process signal monitoring and command input. an advanced graphic compiler for the mce tm is seamlessly integrated into the matlab/simulink environment, while third party jtag bas ed emulator tools are s upported for 8051 developments. irmck311 comes with a small qfp64 pin lead-free package.
irmck311 www.irf.com ? 2007 international rectifier 2 table of contents 1 overview..................................................................................................................... ................. 5 2 irmck311 block diagram and main functions........................................................................ 6 3 pinout....................................................................................................................... .................... 8 4 input/output of irmck311 ..................................................................................................... ... 9 4.1 8051 peripheral interface group......................................................................................... 10 4.2 motion peripheral interface group ..................................................................................... 10 4.3 analog interface group ..................................................................................................... . 11 4.4 power interface group ...................................................................................................... .. 11 4.5 test interface............................................................................................................. .......... 12 5 application connections ...................................................................................................... ..... 13 6 dc characteristics ........................................................................................................... .......... 14 6.1 absolute maximum ratings ............................................................................................... 14 6.2 system clock frequency and power consumption............................................................ 14 6.3 digital i/o dc characteristics............................................................................................ 15 6.4 pll and oscillator dc characteristics............................................................................... 15 6.5 analog i/o dc characteristics ........................................................................................... 16 6.6 under voltage lockout dc characteristics ....................................................................... 17 6.7 aref characteristics....................................................................................................... ... 17 7 ac characteristics ........................................................................................................... .......... 18 7.1 pll ac characteristics ..................................................................................................... . 18 7.2 analog to digital converter ac characteristics ................................................................ 19 7.3 op amp ac characteristics ............................................................................................... 19 7.4 sync to svpwm and a/d conversion ac timing......................................................... 20 7.5 gatekill to svpwm ac timing.................................................................................. 21 7.6 interrupt ac timing ........................................................................................................ ... 21 7.7 i 2 c ac timing .................................................................................................................... 22 7.8 spi ac timing.............................................................................................................. ...... 23 7.8.1 spi write ac timing .................................................................................................... 23 7.8.2 spi read ac timing.................................................................................................... 24 7.9 uart ac timing ............................................................................................................. . 25 7.10 capture input ac timing .......................................................................................... 26 7.11 jtag ac timing ............................................................................................................ 27 7.12 otp programming timing .............................................................................................. 28 8 i/o structure ................................................................................................................ .............. 29 9 pin list..................................................................................................................... .................. 32 10 package dimensions.......................................................................................................... ..... 35 11 part marking information.................................................................................................... ... 36 12 ordering information ........................................................................................................ ..... 36 irmck311 www.irf.com ? 2007 international rectifier 3 table of figures figure 1. typical application block diagram us ing irmc k311 ....................................... 5 figure 2. irmck311 in ternal blo ck diagr am ................................................................... 6 figure 3. irmck311 pin confi guration ............................................................................ 8 figure 4. input/out put of ir mck311................................................................................ 9 figure 5. application connection of irmck311 ............................................................. 13 figure 6. clock frequency vs. power cons umption ...................................................... 14 figure 7 crystal o scillator ci rcuit .................................................................................... 18 figure 8 voltage droop of sample and hol d ................................................................... 19 figure 9 sync to svpwm and a/ d conversion ac ti ming........................................... 20 figure 10 gatekill to svpwm ac timi ng .................................................................... 21 figure 11 interr upt ac timing ........................................................................................ 21 figure 12 i 2 c ac ti ming ................................................................................................ 22 figure 13 spi ac ti ming ............................................................................................... 23 figure 14 spi r ead ac ti ming ...................................................................................... 24 figure 15 uart ac timing............................................................................................ 25 figure 16 capture input ac timing ........................................................................... 26 figure 17 jtag ac ti ming ............................................................................................ 27 figure 18 otp pr ogramming timing ............................................................................. 28 figure 19 all digital i/o ex cept motor pwm output ........................................................... 29 figure 20 reset, gateki ll i/o..................................................................................... 29 figure 21 a nalog i nput...................................................................................................... 30 figure 22 analog operational amplif ier output and aref i/o structure.......................... 30 figure 23 vpp programming pin i/o structure ............................................................. 30 figure 24 vss and avss pi n structure ............................................................................ 31 figure 25 vdd1 and vddc ap pin stru cture .................................................................... 31 figure 26 xtal0/xta l1 pins st ructure.......................................................................... 31 irmck311 www.irf.com ? 2007 international rectifier 4 table of tables table 1. absolute maximum ratings............................................................................................ 14 table 2. system clock frequency............................................................................................... .. 14 table 3. digital i/o dc characteristics ....................................................................................... . 15 table 4. pll dc characteristics ............................................................................................... ... 15 table 5. analog i/o dc characteristics ....................................................................................... 16 table 6. uvcc dc characteristics .............................................................................................. .. 17 table 7. aref dc characteristics .............................................................................................. . 17 table 8. pll ac characteristics ............................................................................................... ... 18 table 9. a/d converter ac characteristics.................................................................................. 19 table 10. current sensing op amp ac characteristics............................................................... 19 table 11. sync ac characteristics............................................................................................. 20 table 12. gatekill to svpwm ac timing ............................................................................ 21 table 13. interrupt ac timing................................................................................................. ..... 21 table 14. i 2 c ac timing .............................................................................................................. 22 table 15. spi write ac timing................................................................................................. ... 23 table 16. spi read ac timing.................................................................................................. ... 24 table 17. uart ac timing...................................................................................................... ... 25 table 18. capture ac timing ................................................................................................. 26 table 19. jtag ac timing...................................................................................................... .... 27 table 20. otp programming timing............................................................................................ 28 table 21. pin list ............................................................................................................ .............. 32 irmck311 www.irf.com ? 2007 international rectifier 5 1 overview irmck311 is a new international rectifier int egrated circuit device primarily designed as a one- chip solution for complete inverter controlled appliance dual motor control applications. unlike a traditional microcontroller or dsp, the irmck311 provides a built-in closed loop sensorless control algorithm using the unique motion control engine (mce tm ) for permanent magnet motors. the mce tm consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port ram to map internal signal nodes. irmck311 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the ic. the sensorless control is the same for both motors with a single shunt current sensing capability. motion control programming is achieved using a dedicated graphical compiler integrated into the matlab/simulink tm development environment. sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. the 8051 microcontroller is equipped with a jtag port to facilitate emulation and debugging tools. figure 1 shows a typical application schematic using irmck311. irmck311 is intended for volume production purpose and contains 64k bytes of otp (one time programming) rom, which can be programmed through a jtag port. for a development purpose use, irmcf311 contains a 48k byte of ram in place of program otp to facilitate an application development work. both irmcf311 and irmck311 come in the same 64-pin qfp package with identical pin configuration to facilitate pc board layout and transition to mass production figure 1. typical application block diagram using irmck311 irmck311 www.irf.com ? 2007 international rectifier 6 2 irmck311 block diagram and main functions irmck311 block diagram is shown in figure 2. 8bit up address/data bus motion control bus figure 2. irmck311 internal block diagram irmck311 contains the following functions for sensorless ac motor control applications: ? motion control engine (mce tm ) o proportional plus integral block o low pass filter o differentiator and lag (high pass filter) o ramp o limit o angle estimate (sensorless control) o inverse clark transformation o vector rotator o bit latch o peak detect o transition irmck311 www.irf.com ? 2007 international rectifier 7 o multiply-divide (signed and unsigned) o divide (signed and unsigned) o adder o subtractor o comparator o counter o accumulator o switch o shift o atan (arc tangent) o function block (any curve fitting, nonlinear function) o 16-bit wide logic operations (and, or, xor, not, negate) o mce tm program and data memory (6k byte). note 1 o mce tm control sequencer ? 8051 microcontroller o three 16-bit timer/counters o 16-bit periodic timer o 16-bit analog watchdog timer o 16-bit capture timer o up to 36 discrete i/os o eleven-channel 12-bit a/d ? five buffered channels (0 ? 1.2v input) ? one unbuffered channel (0 ? 1.2v input) o jtag port (4 pins) o up to three channels of analog output (8-bit pwm) o two uart o i 2 c/spi port o 64k byte note 1 program one-time programmable memory o 2k byte data ram. note 2 note 1: total size of otp memory is 64k byte, however mce program occupies maximum 8k byte which will be loaded into internal ram at a powerup/boot process. therefore only 56k byte otp memory area is usable for 8051 microcontroller. note 2: total size of ram is 8k byte including mce program, mce data, and 8051 data. different sizes can be allocated depending on applications. irmck311 www.irf.com ? 2007 international rectifier 8 3 pinout 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 15 14 13 16 3 12 4 11 5 6 7 8 9 10 2 1 xtal0 xtal1 p1.1/rxd p1.2/txd vdd1 vss vdd2 p1.3/sync/sck p1.4/cap p3.6/rxd1 p3.7/txd1 fpwmvl fpwmul 34 35 36 33 46 37 45 38 44 43 42 41 40 39 47 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vss vdd2 avdd avss ain0 aref p2.7/aopwm1 p2.6/aopwm0 cpwmuh cpwmvh cpwmwh cpwmul cpwmvl cpwmwl cgatekill vdd1 vss ifbco ifbc+ ifbc- pllvss pllvdd reset nc tck p5.3/tdi p5.2/tdo p5.1/tms sda/cs0 scl/so-si/vpp p5.0/pfcgkill pfcpwm vss (top view) fgatekill fpwmwl vac- vac+ vaco ipfco ipfc+ ipfc- ifbfo ifbf+ ifbf- p3.0/int2/cs1 cmext fpwmvh fpwmuh fpwmwh ain1 p3.2/int0 figure 3. irmck311 pin configuration irmck311 www.irf.com ? 2007 international rectifier 9 4 input/output of irmck311 all i/o signals of irmck311 are shown in figure 4. all i/o pins are 3.3v logic interface except a/d interface pins. figure 4. input/output of irmck311 irmck311 www.irf.com ? 2007 international rectifier 10 4.1 8051 peripheral interface group uart interface p1.1/rxd input, receive data to irmck311, can be configured as p1.1 p1.2/txd output, transmit data from irmck311, can be configured as p1.2 p3.6/rxd1 input, 2 nd channel receive data to irmck311, can be configured as p3.6 p3.7/txd1 output, 2 nd channel transmit data from irmck311, can be configured as p3.7 discrete i/o interface p1.3/sync/sck input/output port 1.3, can be configured as sync output or spi clock p1.4/cap input/output port 1.4, can be configured as capture timer input p3.0/int2/cs1 input/output port 3.0, can be configured as external interrupt 2 or spi chip select 1 p3.2/int0 input/output port 3.2, can be configured as external interrupt 0 analog output interface p2.6/aopwm0 input/output, can be configured as 8-bit pwm output 0 with programmable carrier frequency p2.7/aopwm1 input/output, can be configured as 8-bit pwm output 1 with programmable carrier frequency crystal interface xtal0 input, connected to crystal xtal1 output, connected to crystal reset interface reset inout, system reset, needs to be pulled up to vdd1 but doesn?t require external rc time constant i 2 c/spi interface scl/so-si/vpp output, i 2 c clock output, spi so-si sda/cs0 input/output, i 2 c data line, chip select 0 of spi p3.0/int2/cs1 input/output port 3.0, can be configured as external interrupt 2 or spi chip select 1 p1.3/sync/sck input/output port 1.3, can be configured as sync output or spi clock 4.2 motion peripheral interface group pwm cpwmuh output, motor 1 pwm phase u high side gate signal cpwmul output, motor 1 pwm phase u low side gate signal cpwmvh output, motor 1 pwm phase v high side gate signal cpwmvl output, motor 1 pwm phase v low side gate signal cpwmwh output, motor 1 pwm phase w high side gate signal cpwmwl output, motor 1 pwm phase w low side gate signal fpwmuh output, motor 2 pwm phase u high side gate signal fpwmul output, motor 2 pwm phase u low side gate signal irmck311 www.irf.com ? 2007 international rectifier 11 fpwmvh output, motor 2 pwm phase v high side gate signal fpwmvl output, motor 2 pwm phase v low side gate signal fpwmwh output, motor 2 pwm phase w high side gate signal fpwmwl output, motor 2 pwm phase w low side gate signal pfcpwm output, pfc pwm fault cgatekill input, upon assertion, this negates all six pwm signals for motor 1, programmable logic sense p5.0/pfcgkill input, upon assertion, this negates pfcpwm signal, programmable logic sense, can be configured as discrete i/o in which case cgatekill negates pfcpwm fgatekill input, upon assertion, this negates all six pwm signals for motor 2, programmable logic sense 4.3 analog interface group avdd analog power (1.8v) avss analog power return aref buffered 0.6v output cmext unbuffered 0.6v, input to the aref buffer, capacitor needs to be connected. ifbc+ input, operational amplifier positive input for shunt resistor current sensing of motor 1 ifbc- input, operational amplifier negative input for shunt resistor current sensing of motor 1 ifbco output, operational amplifier output for shunt resistor current sensing of motor 1 ifbf+ input, operational amplifier positive input for shunt resistor current sensing of motor 2 ifbf- input, operational amplifier negative input for shunt resistor current sensing of motor 2 ifbfo output, operational amplifier output for shunt resistor current sensing of motor 2 ipfc+ input, operational amplifier positive input for pfc current sensing ipfc- input, operational amplifier negative input for pfc current sensing ipfo output, operational amplifier output for pfc current sensing vac+ input, operational amplifier positive input for pfc ac voltage sensing vac- input, operational amplifier negative input for pfc ac voltage sensing vaco output, operational amplifier output for pfc ac voltage sensing vdc+ input, operational amplifier positive input for dc bus voltage sensing vdc- input, operational amplifier negative input for dc bus voltage sensing ain0/vdco input/output, analog input channel 0 or operational amplifier output for dc bus voltage sensing ain1 input, analog input channel 1 (0-1.2v), needs to be pulled down to avss if unused 4.4 power interface group vdd1 digital power for i/o (3.3v) vdd2 digital power for core logic (1.8v) irmck311 www.irf.com ? 2007 international rectifier 12 vss digital common pllvdd pll power (1.8v) pllvss pll ground return scl/so-si/vpp otp programming supply. can be left open in otp read mode (normal) 4.5 test interface p5.3/tdi input, jtag test data input p5.1/tms input, jtag test mode select tck input, jtag test clock p5.2/tdo output, jtag test data output irmck311 www.irf.com ? 2007 international rectifier 13 5 application connections typical application connection is shown in figur e 5. all components necessary to implement a complete sensorless drive control algorithm are shown connected to irmck311. p1.2/txd p1.1/rxd p1.3/sync/sck xtal0 cpwmuh cpwmul cpwmvh cpwmvl cpwmwh cpwmwl cgatekill ain1 to indoor unit microcontroller (uart) digital i/o control system clock 4 mhz crystal compressor dc bus shunt resistor p2.6/aopwm0 analog output xtal1 p1.4/cap p3.0/int2/cs1 reset scl/so-si/vpp p5.3/tdi jtag control tck p5.1/tms p5.2/tdo 0.6v ifbc+ ifbc- ifbco other analog input (0-1.2v) avdd(1.8v) avss vdd1 vdd2 vss cmext fpwmuh fpwmvh fpwmwh fgatekill pfcgkill pfcpwm fan motor dc bus shunt resistor 0.6v ifbf+ ifbf- ifbfo 0.6v ipfc+ ipfc- ipfco pfc dc bus shunt resistor vac+ vac- vaco ac line voltage optional external voltage reference (0.6v) p2.7/aopwm1 pllvdd(1.8v) pllvss scl/so-si sda/cs0 other communication (i 2 c) pll logic uart0 i 2 c port1 port3 reset pwm0 pwm1 jtag interface low loss space vector pwm low loss space vector pwm pfc pwm s/h s/h s/h 8051 cpu dual port memory (512b) & mce memory (5.5kb) motion control modules motion control sequencer 12bit a/d & mux system clock local ram (2kb) program otp rom (64kb) system reset watchdog timer timer uart1 p3.7/txd1 p3.6/rxd1 to other host (uart) dc bus voltage aref ain0 fpwmul fpwmvl fpwmwl clock divider system clock 6.75v 3.3v 1.8v power figure 5. application connection of irmck311 irmck311 www.irf.com ? 2007 international rectifier 14 6 dc characteristics 6.1 absolute maximum ratings symbol parameter min typ max condition v dd1 supply voltage -0.3 v - 3.6 v respect to vss v dd2 supply voltage -0.3 v - 1.98 v respect to vss v pp otp programming voltage -0.3v - 7.0v respect to vss v ia analog input voltage -0.3 v - 1.98 v respect to avss v id digital input voltage -0.3 v - 3.65 v respect to vss t a ambient temperature -40 ? c - 85 ? c t s storage temperature -65 ? c - 150 ? c table 1. absolute maximum ratings caution: stresses beyond those listed in ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 6.2 system clock frequency and power consumption symbol parameter min typ max unit sysclk system clock 32 - 128 mhz 8051clk 8051 clock - - 32 mhz table 2. system clock frequency power consumption 0 20 40 60 80 100 120 140 160 180 0 20406080100120140 mce frequency (mhz) power (mw) 1.8v 3.3v total power figure 6. clock frequency vs. power consumption irmck311 www.irf.com ? 2007 international rectifier 15 6.3 digital i/o dc characteristics symbol parameter min typ max condition v dd1 supply voltage 3.0 v 3.3 v 3.6 v recommended v dd2 supply voltage 1.62 v 1.8 v 1.98 v recommended v pp otp programming voltage 6.50v 6.75v 7.0v recommended v il input low voltage -0.3 v - 0.8 v recommended v ih input high voltage 2.0 v 3.6 v recommended c in input capacitance - 3.6 pf - (1) i l input leakage current 10 na 1 a v o = 3.3 v or 0 v i ol1 (2) low level output current 8.9 ma 13.2 ma 15.2 ma v ol = 0.4 v (1) i oh1 (2) high level output current 12.4 ma 24.8 ma 38 ma v oh = 2.4 v (1) i ol2 (3) low level output current 17.9 ma 26.3 ma 33.4 ma v ol = 0.4 v (1) i oh2 (3) high level output current 24.6 ma 49.5 ma 81 ma v oh = 2.4 v (1) table 3. digital i/o dc characteristics note: (1) data guaranteed by design. (2) applied to scl/so-si, sda/cs0 pins. (3) applied to p1.1/rxd, p1.2/txd, p1.3/sync/sck, p1.4/cap, p2.6/aopwm0, p2.7/aopwm1, p3.0/int2/cs1, p3.2/int0, p3.6/rxd1, p3.7/txd1, p5.0/pfcgkill, p5.1/tms, p5.2/tdo, p5.3/tdi, cgatekill, fgatekill, cpwmul, cpwmuh, cpwmvl, cpwmvh, cpwmwl, cpwmwh, fpwmul, fpwmuh, fpwmvl, fpwmvh, fpwmwl, fpwmwh, and pfcpwm pins. 6.4 pll and oscillator dc characteristics symbol parameter min typ max condition v pllvdd supply voltage 1.62 v 1.8 v 1.92 v recommended v il osc oscillator input low voltage v pllvss - 0.2* v pllvdd v pllvdd = 1.8 v (1) v ih osc oscillator input high voltage 0.8* v pllvdd v pllvdd v pllvdd = 1.8 v (1) table 4. pll dc characteristics note: (1) data guaranteed by design. irmck311 www.irf.com ? 2007 international rectifier 16 6.5 analog i/o dc characteristics - op amps for current sensing (ifbc+, ifbc-, ifbco, ifbf+, ifbf-, ifbfo, ipfc+, ipfc-, ipfco) c aref = 1nf, c mext = 100nf. unless specified, ta = 25 ? c. symbol parameter min typ max condition v avdd supply voltage 1.71 v 1.8 v 1.89 v recommended v offset input offset voltage - - 26 mv v avdd = 1.8 v v i input voltage range 0 v 1.2 v recommended v outsw op amp output operating range 50 mv (1) - 1.2 v v avdd = 1.8 v c in input capacitance - 3.6 pf - (1) r fdbk op amp feedback resistor 5 k - 20 k requested between op amp output and negative input op gaincl operating close loop gain 80 db - - (1) cmrr common mode rejection ratio - 80 db - (1) i src op amp output source current - 1 ma - v out = 0.6 v (1) i snk op amp output sink current - 100 a - v out = 0.6 v (1) table 5. analog i/o dc characteristics note: (1) data guaranteed by design. rev 1.0 6.6 under voltage lockout dc characteristics - based on avdd (1.8v) unless specified, ta = 25 ? c. symbol parameter min typ max condition uv cc+ uvcc positive going threshold 1) 1.53 v 1.66 v 1.71 v v dd1 = 3.3 v uv cc- uvcc negative going threshold 1.52 v 1.62 v 1.71 v v dd1 = 3.3 v uv cc h uvcc hysteresys - 40 mv - table 6. uvcc dc characteristics note: 1) data guaranteed by design. 6.7 aref characteristics c aref = 1nf, c mext = 100nf. unless specified, ta = 25 ? c. symbol parameter min typ max condition v aref aref output voltage 495 mv 600 mv 700 mv v avdd = 1.8 v v o load regulation (v dc -0.6) - 1 mv - (1) psrr power supply rejection ratio - 75 db - (1) table 7. aref dc characteristics note: (1) data guaranteed by design. irmck311 www.irf.com ? 2007 international rectifier 18 7 ac characteristics 7.1 pll ac characteristics symbol parameter min typ max condition f clkin crystal input frequency 3.2 mhz 4 mhz 60 mhz (1) (see figure below) f pll internal clock frequency 32 mhz 50 mhz 128 mhz (1) f lwpw sleep mode output frequency f clkin 256 - - (1) j s short time jitter - 200 psec - (1) d duty cycle - 50 % - (1) t lock pll lock time - - 500 sec (1) table 8. pll ac characteristics note: (1) data guaranteed by design. xtal r 1 =1m r 2 =10 c 1 =30pf c 2 =30pf figure 7 crystal oscillator circuit irmck311 www.irf.com ? 2007 international rectifier 19 7.2 analog to digital converter ac characteristics unless specified, ta = 25 ? c . symbol parameter min typ max condition t conv conversion time - - 2.05 sec (1) t hold sample/hold maximum hold time - - 10 sec voltage droop 15 lsb (see figure below) table 9. a/d converter ac characteristics note: (1) data guaranteed by design. t hold voltage droop t sample s/h voltage input voltage figure 8 voltage droop of sample and hold 7.3 op amp ac characteristics - op amps for current sensing (ifbc+, ifbc-, ifbco, ifbf+, ifbf-, ifbfo, ipfc+, ipfc-, ipfco) unless specified, ta = 25 ? c. symbol parameter min typ max condition op sr op amp slew rate - 10 v/ sec - v avdd = 1.8 v, cl = 33 pf (1) op imp op input impedance - 10 8 ? - (1) t set settling time - 400 ns - v avdd = 1.8 v, cl = 33 pf (1) table 10. current sensing op amp ac characteristics note: (1) data guaranteed by design. irmck311 www.irf.com ? 2007 international rectifier 20 7.4 sync to svpwm and a/d conversion ac timing sync iu,iv,iw t wsync t dsync1 ainx t dsync2 pwmux,pwmvx,pwmwx t dsync3 figure 9 sync to svpwm and a/d conversion ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wsync sync pulse width - 32 - sysclk t dsync1 sync to current feedback conversion time - - 100 sysclk t dsync2 sync to ain0-6 analog input conversion time - - 200 sysclk (1) t dsync3 sync to pwm output delay time - - 2 sysclk table 11. sync ac characteristics note: (1) ain1 through ain6 channels are converted once every 6 sync events irmck311 www.irf.com ? 2007 international rectifier 21 7.5 gatekill to svpwm ac timing figure 10 gatekill to svpwm ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wgk gatekill pulse width 32 - - sysclk t dgk gatekill to pwm output delay - - 100 sysclk table 12. gatekill to svpwm ac timing 7.6 interrupt ac timing figure 11 interrupt ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t wint int0, int1 interrupt assertion time 4 - - sysclk t dint int0, int1 latency - - 4 sysclk table 13. interrupt ac timing irmck311 www.irf.com ? 2007 international rectifier 22 7.7 i 2 c ac timing scl sda t i2st1 t i2st2 t i2wsetup t i2clk t i2whold t i2rsetup t i2rhold t i2clk t i2en1 t i2en2 figure 12 i 2 c ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t i2clk i 2 c clock period 10 - 8192 sysclk t i2st1 i 2 c sda start time 0.25 - - t i2clk t i2st2 i 2 c scl start time 0.25 - - t i2clk t i2wsetup i 2 c write setup time 0.25 - - t i2clk t i2whold i 2 c write hold time 0.25 - - t i2clk t i2rsetup i 2 c read setup time i 2 c filter time (1) - - sysclk t i2rhold i 2 c read hold time 1 - - sysclk table 14. i 2 c ac timing note: (1) i 2 c read setup time is determined by the programmable filter time applied to i 2 c communication. irmck311 www.irf.com ? 2007 international rectifier 23 7.8 spi ac timing 7.8.1 spi write ac timing figure 13 spi ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csdelay cs to data delay time - - 10 nsec t wrdelay clk falling edge to data delay time - - 10 nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 15. spi write ac timing irmck311 www.irf.com ? 2007 international rectifier 24 7.8.2 spi read ac timing figure 14 spi read ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t spiclk spi clock period 4 - - sysclk t spiclkht spi clock high time - 1/2 - t spiclk t spiclklt spi clock low time - 1/2 - t spiclk t csrd cs to data delay time - - 10 nsec t rdsu spi read data setup time 10 - - nsec t rdhold spi read data hold time 10 - - nsec t cshigh cs high time between two consecutive byte transfer 1 - - t spiclk t cshold cs hold time - 1 - t spiclk table 16. spi read ac timing irmck311 www.irf.com ? 2007 international rectifier 25 7.9 uart ac timing txd rxd data and parity bit start bit t baud stop bit t uartfil figure 15 uart ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t baud baud rate period - 57600 - bit/sec t uartfil uart sampling filter period (1) - 1/16 - t baud table 17. uart ac timing note: (1) each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 t baud . if three sampled values do not agree, then uart noise error is generated. irmck311 www.irf.com ? 2007 international rectifier 26 7.10 capture input ac timing figure 16 capture input ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t capclk capture input period 8 - - sysclk t caphigh capture input high time 4 - - sysclk t caplow capture input low time 4 - - sysclk t crdelay capture falling edge to capture register latch time - - 4 sysclk t cldelay capture rising edge to capture register latch time - - 4 sysclk t intdelay capture input interrupt latency time - - 4 sysclk table 18. capture ac timing irmck311 www.irf.com ? 2007 international rectifier 27 7.11 jtag ac timing tck tdo t jhigh t jclk t co t jlow t jsetup t jhold tdi/tms figure 17 jtag ac timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t jclk tck period - - 50 mhz t jhigh tck high period 10 - - nsec t jlow tck low period 10 - - nsec t co tck to tdo propagation delay time 0 - 5 nsec t jsetup tdi/tms setup time 4 - - nsec t jhold tdi/tms hold time 0 - - nsec table 19. jtag ac timing irmck311 www.irf.com ? 2007 international rectifier 28 7.12 otp programming timing figure 18 otp programming timing unless specified, ta = 25 ? c. symbol parameter min typ max unit t vps vpp setup time 10 - - nsec t vph vpp hold time 15 - - nsec table 20. otp programming timing irmck311 www.irf.com ? 2007 international rectifier 29 8 i/o structure the following figure shows the motor pwm and digital i/o structure except the motor pwm output figure 19 all digital i/o except motor pwm output the following figure shows reset and gatekill i/o structure. figure 20 reset, gatekill i/o irmck311 www.irf.com ? 2007 international rectifier 30 the following figure shows the analog input structure. 100 6.0v 6.0v analog input pin avss analog circuit avdd figure 21 analog input the following figure shows all analog operational amplifier output pins and aref pin i/o structure. 6.0v 6.0v analog output pin avss analog circuit 1.8v figure 22 analog operational amplifier output and aref i/o structure the following figure shows the vpp pin i/o structure figure 23 vpp programming pin i/o structure the following figure shows the vss, avss and pllvss pin structure irmck311 www.irf.com ? 2007 international rectifier 31 figure 24 vss, avss and pllvss pin structure the following figure shows the vdd1, vdd2, avdd and pllvdd pin structure pin vss 6.0v figure 25 vdd1, vdd2, avdd and pllvdd pin structure the following figure shows the xtal0 and xtal1 pins structure figure 26 xtal0/xtal1 pins structure irmck311 www.irf.com ? 2007 international rectifier 32 9 pin list pin number pin name internal ic pull-up /pull-down pin type description 1 xtal0 i crystal input 2 xtal1 o crystal output 3 p1.1/rxd i/o discrete programmable i/o or uart receive input 4 p1.2/txd i/o discrete programmable i/o or uart transmit output 5 p1.3/sync/ sck i/o discrete programmable i/o or sync output or spi clock 6 p1.4/cap i/o discrete programmable i/o or capture timer input 7 vdd2 p 1.8v digital power 8 vss p digital common 9 vdd1 p 3.3v digital power 10 fgatekill i fan pwm shutdown input, 2- sec digital filter, configurable either high or low true. 11 fpwmwl 70 k ? pull up o fan pwm gate drive for phase w low side, configurable either high or low true 12 fpwmwh 70 k ? pull up o fan pwm gate drive for phase w high side, configurable either high or low true 13 fpwmvl 70 k ? pull up o fan pwm gate drive for phase v low side, configurable either high or low true 14 fpwmvh 70 k ? pull up o fan pwm gate drive for phase v high side, configurable either high or low true 15 fpwmul 70 k ? pull up o fan pwm gate drive for phase u low side, configurable either high or low true 16 fpwmuh 70 k ? pull up o fan pwm gate drive for phase u high side, configurable either high or low true 17 p2.6/ aopwm0 i/o discrete programmable i/o or analog output 0 (pwm) 18 p2.7/ aopwm1 discrete programmable i/o or analog output 1 (pwm) 19 vdd2 p 1.8v digital power 20 vss p digital common 21 ifbf- i fan single shunt current sensing op amp input (-) 22 ifbf+ i fan single shunt current sensing op amp input (+) 23 ifbfo o fan single shunt current sensing op amp output 24 ain0 i analog input channel 0, 0-1.2v range, needs to be pulled down to avss if unused 25 avdd p 1.8v analog power 26 avss p analog common 27 ain1 i analog input channel 1, 0-1.2v range, needs to be pulled down to avss if unused 28 aref o analog reference voltage output (0.6v) 29 cmext o unbuffered analog reference voltage output (0.6v) irmck311 www.irf.com ? 2007 international rectifier 33 pin number pin name internal ic pull-up /pull-down pin type description 30 ifbc- i compressor single shunt current sensing op amp input (-) 31 ifbc+ i compressor single shunt current sensing op amp input (+) 32 ifbco o compressor single shunt current sensing op amp output 33 vac- i ac input voltage sensing op amp input (-) 34 vac+ i ac input voltage sensing op amp input (+) 35 vaco o ac input voltage sensing op amp output 36 ipfco o pfc shunt current sensing op amp output 37 ipfc+ i pfc shunt current sensing op amp input (+) 38 ipfc- i pfc shunt current sensing op amp input (-) 39 vss p digital common 40 vdd1 p 3.3v digital power 41 cgatekill i compressor pwm shutdown input, 2- sec digital filter, configurable either high or low true. 42 cpwmwl 70 k ? pull up o compressor pwm gate drive for phase w low side, configurable either high or low true 43 cpwmwh 70 k ? pull up o compressor pwm gate drive for phase w high side, configurable either high or low true 44 cpwmvl 70 k ? pull up o compressor pwm gate drive for phase v low side, configurable either high or low true 45 cpwmvh 70 k ? pull up o compressor pwm gate drive for phase v high side, configurable either high or low true 46 cpwmul 70 k ? pull up o compressor pwm gate drive for phase u low side, configurable either high or low true 47 cpwmuh 70 k ? pull up o compressor pwm gate drive for phase u high side, configurable either high or low true 48 p3.0/int2 i/o discrete programmable i/o or int2 digital input 49 p5.0/ pfcgkill i discrete programmable i/o or pfc pwm shutdown input, 2- sec digital filter, configurable either high or low true. 50 pfcpwm 70 k ? pull up o pfc pwm gate drive, configurable either high or low true 51 p3.2/int0 i/o discrete programmable i/o or int0 input 52 p3.6/rxd1 i/o discrete programmable i/o or 2 nd uart receive input 53 p3.7/txd1 i/o discrete programmable i/o or 2 nd uart transmit output 54 vss p digital common 55 scl/so- si/vpp i/o p i 2 c clock output or spi data or otp programming voltage 56 sda/cs0 i/o i 2 c data or spi chip select 0 57 p5.1/tms i/o discrete programmable i/o or jtag test mode select irmck311 www.irf.com ? 2007 international rectifier 34 pin number pin name internal ic pull-up /pull-down pin type description 58 p5.2/tdo i/o discrete programmable i/o or jtag port test data output 59 p5.3/tdi i/o discrete programmable i/o or jtag test data input 60 tck i jtag test clock 61 n.c. - no connection 62 reset i/o reset , low true, schmitt trigger input 63 pllvdd p 1.8 v pll power 64 pllvss p pll ground table 21. pin list irmck311 www.irf.com ? 2007 international rectifier 35 10 package dimensions irmck311 www.irf.com ? 2007 international rectifier 36 11 part marking information 12 ordering information lead-free part in 64-lead qfp moisture sensitivity rating ? msl3 part number order quantities irmck311ty 1600 parts on trays (160 parts per tray) in dry pack the lqfp-100 is msl3 qualified this product has been designed and qualified for the industrial level qualification standards can be found at www.irf.com |
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